Computer Architecture (1996-2021)

Chair of Computer Architecture Group

History and Research

The Computer Architecture Group (CAG) has dedicated its research and teaching activities to the understanding and design of complex hardware/software systems, with a special interest in parallel computer architecture and high performance computing. As system architects, we covered not only the operation principles but also the technology and software to build working prototype systems. The group’s expertise covered the design space analysis and hardware design of processors, devices and interconnection networks, as well as the development of the corresponding software ecosystem (e. g. kernel drivers and communication libraries).

The CAG’s research interests cover all levels of the system design, starting at the application programming interface, e.g. MPI, through the efficient design of device drivers finishing at custom build hardware devices based on standard cells and FP- GAs. Goals of the applied research activities were to cover a broad range of methodologies for the design of complete high performance systems with the possibility to optimize every level and educate students on various real world topics. The CAG concluded its research activity in March 2021.

Selection of Past Research Projects

EXTOLL - Extreme Low Latency Interconnect

EXTOLL introduces a new interconnection network architecture for High-Performance Computing, which brings a rich set of features to the HPC application space. The EXTOLL solution integrates host-interface, network interface controller and network functions within a single chip. This single chip solution enables power efficiency and lower total cost of ownership.

GreenICE - Immersion cooled electronics

The GreenICE System is based on the principle of 2-phase immersion cooling. The electronic assemblies, such as server modules, are arranged standing up in a chassis filled with 3M NovecTM 649 Engineered Fluid.

openHMC - An open-source Hybrid Memory Cube controller

openHMC is a vendor-agnostic, AXI-4 compliant Hybrid Memory Cube (HMC) controller that can be parameterized to different data-widths, external lane-width requirements, and clock speeds depending on speed and area requirements. The main objective of developing the HMC controller is to lower the barrier for others to experiment with the HMC, without the risks of using commercial solutions. Project data and documentation can be found here.

DEEP - Extreme Scale Technologies (DEEP - EST)

The Modular Supercomputer Architecture (MSA) developed in the DEEP-EST research project is a blueprint for heterogeneous HPC systems supporting the divergent computation and dataprocessing requirements of high performance compute and data analytics with highest efficiency and scalability. The MSA isbased on the Cluster-Booster architecture developed in the previous DEEP and DEEP-ER projects. The MSA interconnection network is based on EXTOLL, encapsulated in a dense form factor box called FabriCube. In cooperation with EXTOLL, the Computer Architecture Group is responsible for the design and implementation of two key components, which serve two different use cases:

(1) Network Attached Memory (NAM) provides network-speed access up to a maximum of 64 TB non-volatile storage. It can serve as an inter- mediate storage target to, for example, hold machine learning training data. Its functionality is complemented by application specific processing elements to execute small compute kernels.

(2) The Global Collective Engine (GCE) is equipped with two DDR4 memory DIMMs. These function as a buffer for data elements required to process global collective operations “in the network”. Collective operations are among the most commonly used communication patterns in HPC applications. Hence, accelerating these operations will likely improve application runtimes and system efficiency. The DEEP-EST project has officially started in July 2017 and concluded its work in March 2021. Further information is available at here.

The Human Brain Project

The Human Brain Project (HBP) aims to understand how the inconceivably efficient system of the human brain works. For this purpose, it uses the method of synthesis biology. This means that it tries to understand the biological system from the bottom-up direction instead of using the conventional analytic top-down methodology. The BrainScaleS system at the Kirchhof-Institute for Physics (KIP) in Heidelberg is part of the HBP and pursues this goal by developing a neuromorphic analog hardware system in combination with a conventional computing cluster. Up to now, the communication FPGAs have been connected through an Ethernet network using USB 3.0 cables. In collaboration with the Computer Architecture Group, the KIP develops a new network interface for the FPGAs controlling the data communication between the neuromorphic hardware chips and the conventional digital system. This new network interface will utilize the benefits of the EXTOLL network technology, a high- performance interconnection network, which is optimized for low latency and high message rates. Further information is available here.

Cadence Academic Network

The Cadence Academic Network was launched in 2007. The aim is to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence. A knowledge network among selected universities, research institutes, industry advisors, and Cadence facilitates the sharing of technology expertise in the areas of verification, design, and implementation of microelectronic systems.The Heidelberg University, specifically the Computer Architecture Group, is a member of this network as the Lead Institution for Advanced Verification Methodology.

Publications

1999-2009:

2010-2019

Further Information

The Chairholder Prof. Dr. Ulrich Brüning can be reached by e-mail via ulrich.bruening@ziti.uni-heidelberg.de.