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Research Group Next generation network interfaces

Goal of the research group Next Generation Network Interfaces is to push research in the field of interconnection networks for parallel computing in its entirety. The focus hereby lies on improving the performance of so called computing clusters. An essential aspect which needs to be optimized is communication latency.

The performance of the complete system relies on the technologies and protocols used on the network-, link- and physical layer. In the past, the computer architecture group developed the EXTOLL low latency interconnect network, which offers optimized hardware functional units for host interface as well as network communication. Paired with an efficient software stack from kernel drivers up to MPI this infrastructure sets the basis for further projects pursued by this research group.


Figure 1: EXTOLL netwok controller placed on an FPGA



Network Attached Memory

In the field of next generation memory technologies this research group is investigating so called Network Attached Memory (NAM). NAM is meant to function as a globally accessible memory within the Extoll interconnection network. Complemented by computational functional units, with NAM it will be possible to offload calculations or other operations done on the memory content, therefore significantly reducing network traffic, processor usage, and also power consumption. The goal is to bring calculations closer to globally shared memory.  

The first prototype of the NAM is currently under evaluation within the Dynamical Exascale Entry Platform – Extended Reach (DEEP-ER) project (Figure 2).  In this context, the NAM provides ‘intelligence’ to enable system-level check-pointing or emulation of non-volatile memory technologies for example.

The NAM itself consists of two parts: A Hybrid Memory Cube (HMC) as the actual memory, and an FPGA that implements three main functions: an EXTOLL Network Interface Controller (NIC), an HMC host controller, and the NAM ‘intelligence’.


Figure 2: DEEP_ER project overview


Versatile Multigigabit Transceiver Architecture

Almost every state of the art high-speed connection uses SerDes (Serialer/Deserializer) technology. Therefore, even if a SerDes only serves as a “fast I/O port” for the actual functions of interest realized in an integrated circuit (IC), it is a key component of the physical communication layer.

The OpenMGT project is a research project aiming to provide an architectural implementation of a multigigabit transceiver design. Its goal is to provide simulation models of various scope and complexity as well as performance metrics against which an actual physical implementation can be verified. Finally a physical reference implementation as a proof of concept is intended.

The extendable and modular transceiver architecture can be used to study possibilities for future power saving min interconnection networks when using  tighter higher level protocol and physical layer interaction.

By providing a well-documented and versatile model infrastructure, the architecture will also ease custom IC designs in various different research projects. This is especially true in cases where transceivers are merely required as system building block and major research emphasis does not lie on efficient transceiver architecture itself. This may be the case for groups building custom high speed data processing and communication systems or for researchers focusing on advanced physical transmission techniques who are in need of high speed data generation and detection circuits when building highly integrated systems.

OpenMGT will be based on two driving principles to achieve necessary flexibility: The architecture is structured hierarchically with a top-down implementation methodology. This will be reflected in the degree of complexity of the transceiver models. The desired level can thus be chosen to be particularly efficient for a given simulation scope. Furthermore, all design choices are based on a “digital first” approach. Wherever feasible and sensible, a digital implementation will be preferred over an analog counterpart. This aims to make the transceiver architecture more easily portable and viable choice even for more advanced technology nodes in the future.

For the OpenMGT project the research group will cooperate with the group for Detektortechnologie und ASIC Design of the Institut für Prozessdatenverarbeitung und Elektronik (IPE) at Karlsruher Institut für Technology (KIT).


  • Markus Mueller (Speaker), email: markus.mueller {at} ziti.uni-heidelberg.de
  • Juri Schmidt, email: juri.schmidt {at} ziti.uni-heidelberg.de
  • Maximillian Thuermer, email: maximillian.thuemer {at} ziti.uni-heidelberg.de
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