FPGA Ignite Summer School 2023
Heidelberg University, July 31 – August 4
Please follow us here to the new website with Zoom links and materials
Kindly supported by Carl-Zeiss-Stiftung
The FPGA Ignite Summer School series is a forum for bringing together established and new researchers in the field of reconfigurable computing and FPGAs.
The goal is to identify and form new trends, educate people and facilitating collaborations within the reconfigurable computing community.
FPGA Ignite 2023 will have a strong emphasis on open-source hardware and tools.
Topics include HLS tools, Logic Synthesis (including interesting specialties for research), FPGA Place&Route as well as FPGA chip design.
During a hackathon on the last day, attendees will design an FPGA with custom tiles that will be manufactured in Sky130 technology.
Attendees will receive a board with that chip some time after the event.
Program (tentative - small changes may apply)
Day 1 (July 31st) |
|
from 9:30 | Registration and welcome coffee |
10:00 – 10:25 | Welcome to Heidelberg and FPGA Ignite 2023 |
10:30 – 12:30 | Lightning talks |
12:30 – 13:45 | Lunch (Bräustüble) |
13:45 – 15:00 | Keynote LegUp High-Level Synthesis and its Commercialization Prof. Jason Anderson, University of Toronto, CA |
15:00 – 16:00 | Attendee Poster Session (details TBD) |
16:00 | Hike to Neuburg Abbey (over the Philosophers’ Walk) and dinner (18:00) at Klostergarten |
Day 2 (Aug.1st) |
High-Level-Synthesis (Jason Anderson) |
8:45 | Registration |
9:00 – 12:30 |
Morning classes
|
12:30 – 13:45 | Lunch (Rosetto) |
13:45 – 17:00 | Afternoon labs (Coffee at 15:15) |
18:00 | Dinner (Marstall Mensa) |
19:30 – 21:00 | Guided City Tour (Start: Universitätsplatz) |
Day 3 (Aug. 2nd) | Logic Synthesis with Yosys (Nina Engelhardt, YosysHQ) |
8:45 | Registration |
9:00 – 12:30 |
Morning classes
|
12:30 – 13:45 | Lunch (Mensa) |
13:45 – 17:00 | Afternoon labs (Coffee at 15:15) |
20:00 | Evening Event (Kulturbrauerei Heidelberg) |
Day 4 (Aug. 3rd) | |
8:45 | Registration |
09:00 – 10:30 (Coffee 10:30) |
nextpnr (Myrtle Shah, Heidelberg University)
|
11:00 – 12:30 | FABulous (Dirk Koch, Heidelberg University)
|
12:30 – 13:45 | Lunch (Bräustüble) |
13:45 – 16:00 | Open-source ASIC design (Nguyen Dao, Gavaskar)
|
16:00 – 17:00 | Labs |
19:00 | Dinner |
Day 5 (Aug. 4th) | Hackathon |
09:00 – 10:30 | From Zero to ASIC in a nutshell (Matt Venn) |
from 10:30 | Happy FPGA Hacking (design a custom FPGA Tile; supported by Nguyen, Myrtle, and Gavaskar) |
16:30 | Pizza and Best Design Award |
Registration
Thanks to support from Carl-Zeiss-Stiftung, FPGA Ignite 2023 is free of charge to attend.
(attendees will have to arrange/pay travel and accommodation on their own. The Central Hotel and the Ibis are in walking distance to the main train station and the venue and usually reasonably priced)
All FPGA Ignite 2023 places have been taken, and we cannot accept any further application.
Thanks for your understanding
Organizers
Dirk Koch, Alexander Schubert, Myrtle Shah,and Riadh Ben Abdelhamid, Novel Computing Technologies, ZITI, Heidelberg University
Daniel Ziener, Computer Architecture and Embedded Systems, TU Ilmenau
Venue
The first day, the classes and the Hackathon will take place at the Käthe Leichter Forum (Graduiertenakademie)
Address: Im Neuenheimer Feld 370, 69120 Heidelberg
Map
Main Sponsor
Carl-Zeiss-Stiftung
Further support is proved through the UK EPSRC programme grant FORTE (grant agreement EP/R024642/1)
Interested in supporting FPGA Ignate 2023 (e.g., supporting travel grants, the evening events, the hackarthon...)?
Then do not hesitate and This email address is being protected from spambots. You need JavaScript enabled to view it..
Hotels
It is usually best to directly book a hotel through a major portal.
Hotel Central and the IBIS are close to the main train station and in walking distance to the campus.
From the old city, you can take bus 31 or 32 from Universitätsplatz to stop Kampus Neuenheimer Feld
Contact
Prof. Dirk Koch |
Keynote
Lecturers
Jason Anderson is a Professor in the Dept. of Electrical and Computer Engineering, University of Toronto, where he holds the Jeffrey Skoll Endowed Chair. His research interests include design methodologies, architecture, circuits and applications of reconfigurable hardware. Prior to joining the university, he spent 10 years in the industry at Xilinx, Inc., in San Jose, CA and Toronto, where he worked on commercial CAD tools for Xilinx FPGAs, both as an individual contributor and later, as a manager. He is an inventor on over 30 issued U.S. patents, has co-authored 4 book chapters, and over 100 papers in peer-reviewed journals and international symposia. In 2015, he co-founded LegUp Computing Inc. with three former graduate students to commercialize his team’s research on high-level synthesis (HLS). The LegUp startup company received investment funding from Intel Capital in 2018, and was acquired in October 2020 by Microchip Technology. LegUp HLS technology has been commercialzed as SmartHLS and is available to target Microchip FPGAs. He is an IEEE Fellow (class of 2023).
Nina Engelhardt is CEO of YosysHQ while also being involved heavily in the technical side of Yosys. (With a background in FPGA-based graph processing they are used to dealing with interconnected systems that have a lot of things going on simultaneously.)
Nina manages the twitter account of their two cats, and galvanize their co-workers by seamlessly switching between 4 languages.
Matthew Venn is a science & technology communicator and electronic engineer. He brings 20 years of engineering experience to create excellent and innovative learning experiences for people all over the world. Matt designed the Zero to ASIC Course.
Websites
https://www.zerotoasiccourse.com/
https://github.com/mattvenn
https://twitter.com/matthewvenn
Myrtle Shah is the maintainer of the open source nextpnr place-and-route tool, providing an alternative flow for several commercial FPGA families with thousands of users worldwide.
After some time working as a contractor, they are currently a researcher and PhD student at Heidelberg University, working on further developing the opportunities for open infrastructure in the FPGA ecosystem.
K. Gavaskar is a post-doctoral researcher with ZITI, Heidelberg Universit. He obtained his BE degree in Electronics and Communication Engineering from Sri Ramakrishna Institute of Technology, Tamil Nadu, India, in 2011, his M.E. degree in VLSI Design from Bannari Amman Institute of Technology, Tamil Nadu, India, in 2013, and completed his Ph.D. degree in the area of Low Power VLSI Memory Design at Anna University, Chennai, India, in 2020. He has 9.9 years of teaching experience at Kongu Engineering College, Tamil Nadu, India. He has published more than 40 papers in journals and conferences. His area of interest includes ASIC implementation of analog and digital circuit designs.
Nguyen Dao obtained a Bachelor's degree in Vietnam in 2007. He began his professional journey at Renesas Electronic Vietnam, where he served as a senior hardware design engineer from 2007 to 2010. He then earned both a Master's degree (2012) and a Ph.D. degree (2017) in Sydney, Australia. In 2018, Nguyen joined The University of Manchester as a Research Associate. During this period, his focus was on the integration of memristor ReRAM on Digital Reconfiguration Systems - FPGAs. After his tenure at the university, he worked with Withsecure Ltd. for a year (2022) before joining Agile Analog Ltd. as a staff hardware design engineer. His research and work focus on ASIC designs and implementations, aiming to make significant contributions to the field of ASIC-FPGA designs and continue driving innovation in the industry.