Datum und Uhrzeit:
Ort: Seminar room OMZ (U013, INF 350, floor -1)
Title: Multi-Domain Architectures for Processing-Using-Memory
Abstract: With the explosion of data processing in modern applications, there has been a concerted effort to design new computer architectures that overcome the limitations of von Neumann computing. An emerging focus of these efforts is processing-using-memory (PUM), or in-memory computing, which attempts to eliminate most CPU–memory data movement bottlenecks by repurposing memory arrays to directly perform computational operations. Perhaps unsurprisingly, the majority of recent work on PUM has focused on accelerating machine learning, but this concentration has neglected the many other application domains that demonstrate the potential for large benefits with PUM.
In this talk, I will discuss my research group’s efforts on designing PUM-based systems that have multi-domain applicability. Starting from an overview of how to perform application-driven PUM design, I will discuss two of our recent architectures. The RACER architecture shows how with Boolean-based wide vector PUM operations designed for general-purpose computing, we can deliver 100+x improvements in both performance and energy across many application domains, compared to a state-of-the-art CPU. Notably, RACER’s architecture can be used on top of a wide range of memory technologies. The ANVIL architecture shows how with bulk associative search PUM operations, we can enable PUM operations for large data sets that exceed the capacities of most main memories, by performing PUM in solid-state drives. ANVIL’s search-based PUM can accelerate any name–value data pair data structure, making it highly versatile. With both RACER and ANVIL, I will illustrate why cross-stack integration is essential to the future of PUM architectures
CV: Saugata Ghose is an assistant professor in the Siebel School of Computing and Data Science at the University of Illinois Urbana-Champaign, where he leads the ARCANA Research Group. He holds M.S. and Ph.D. degrees in electrical and computer engineering from Cornell University, and dual B.S. degrees in computer science and in computer engineering from Binghamton University, State University of New York. He has been recognized with an Intel Rising Star Faculty Award, induction into the ISCA and HPCA Halls of Fame, and a Wimmer Faculty Fellowship at Carnegie Mellon University. Several of his works have been winners or finalists for best-of-venue awards, and one was a finalist for the 2022 Intel Hardware Security Academic Award. His current research interests include data-oriented computer architectures and systems, new interfaces between systems software and hardware, energy-efficient memory and storage, and architectures for emerging platforms and domains. For more information, please visit his website.