Lecturers


Jason Anderson is a Professor in the Dept. of Electrical and Computer Engineering, University of Toronto, where he holds the Jeffrey Skoll Endowed Chair.  His research interests include design methodologies, architecture, circuits and applications of reconfigurable hardware.  Prior to joining the university, he spent 10 years in the industry at Xilinx, Inc., in San Jose, CA and Toronto, where he worked on commercial CAD tools for Xilinx FPGAs, both as an individual contributor and later, as a manager.  He is an inventor on over 30 issued U.S. patents, has co-authored 4 book chapters, and over 100 papers in peer-reviewed journals and international symposia.  In 2015, he co-founded LegUp Computing Inc. with three former graduate students to commercialize his team’s research on high-level synthesis (HLS).  The LegUp startup company received investment funding from Intel Capital in 2018, and was acquired in October 2020 by Microchip Technology.  LegUp HLS technology has been commercialzed as SmartHLS and is available to target Microchip FPGAs.  He is an IEEE Fellow (class of 2023).


Nina Engelhardt is CEO of YosysHQ while also being involved heavily in the technical side of Yosys. (With a background in FPGA-based graph processing they are used to dealing with interconnected systems that have a lot of things going on simultaneously.)

Nina manages the twitter account of their two cats, and galvanize their co-workers by seamlessly switching between 4 languages.


Matthew Venn is a science & technology communicator and electronic engineer. He brings 20 years of engineering experience to create excellent and innovative learning experiences for people all over the world. Matt designed the Zero to ASIC Course.
Websites
   https://www.zerotoasiccourse.com/
   https://github.com/mattvenn
   https://twitter.com/matthewvenn



Myrtle Shah is the maintainer of the open source nextpnr place-and-route tool, providing an alternative flow for several commercial FPGA families with thousands of users worldwide.

After some time working as a contractor, they are currently a researcher and PhD student at Heidelberg University, working on further developing the opportunities for open infrastructure in the FPGA ecosystem.



K. Gavaskar is a post-doctoral researcher with ZITI, Heidelberg Universit. He obtained his BE degree in Electronics and Communication Engineering from Sri Ramakrishna Institute of Technology, Tamil Nadu, India, in 2011, his M.E. degree in VLSI Design from Bannari Amman Institute of Technology, Tamil Nadu, India, in 2013, and completed his Ph.D. degree in the area of Low Power VLSI Memory Design at Anna University, Chennai, India, in 2020. He has 9.9 years of teaching experience at Kongu Engineering College, Tamil Nadu, India. He has published more than 40 papers in journals and conferences. His area of interest includes ASIC implementation of analog and digital circuit designs.











Nguyen Dao obtained a Bachelor's degree in Vietnam in 2007. He began his professional journey at Renesas Electronic Vietnam, where he served as a senior hardware design engineer from 2007 to 2010. He then earned both a Master's degree (2012) and a Ph.D. degree (2017) in Sydney, Australia. In 2018, Nguyen joined The University of Manchester as a Research Associate. During this period, his focus was on the integration of memristor ReRAM on Digital Reconfiguration Systems - FPGAs. After his tenure at the university, he worked with Withsecure Ltd. for a year (2022) before joining Agile Analog Ltd. as a staff hardware design engineer. His research and work focus on ASIC designs and implementations, aiming to make significant contributions to the field of ASIC-FPGA designs and continue driving innovation in the industry.