The term Field Programmable Gate Arrays (FPGAs) describe both devices and a kind of Technology. Opposed to ASICs, where logic is fixed for a specific function, FPGAs allow for the customization of chips after their production. In contrast to Software programming, where a developer writes and optimizes code for a given architecture (e.g., your x86 or RISC-V core), FPGA developers control and optimize the hardware architecture in the first place. This allows for drastically better performance and energy efficiency.  

Note that this course is NOT about developing FPGA user circuits and learning how to use vendor design tools (there are other courses dealing with this). This course is concerned about the DESIGN of FPGAs and the TOOLs themselves, including the architectural details, algorithms and data structures used. Of course, this course will provide you with a deeper understanding of FPGAs (and hardware in general) and will help you to become a better hardware (and software) designer.

Course leaders:   Prof. Dirk Koch & Myrtle Shah

Teaching language:

all material will be provided in English language, classes can be in German language on request

Format: 

classes and exercises (we will have more classes in the beginning of the unit and spend more time on labs and the project at the end of the unit)

Assessment: 

50% project and 50% oral exam

Recommended knowledge: 

Hardware design (Verilog or VHDL), Algorithms and data structures, FPGA Basics

Moodle link: https://moodle.uni-heidelberg.de/course/view.php?id=19313

1) Introduction - Programmability

• Hardware programmabillity: reconfigurable logic and routing structures
• Software versus Hardware programmability
• The FPGA Ecosystem

2) FPGA Deep Dive

• Why Look-up Tables (LUTs)? And how?
• Logic cell design (support for arithmetic, wide logic gates)
• FPGA fabric design factors

3) Specialized blocks

• FPGA memory hierarchy (capacity, features)
• Arithmetic blocks (DSPs, ALUs, special functions)
• I/Os (double data I/Os, SerDes, complex I/Os)

4) Multiplexers and Multiplexing 

• Standard cell versus passgate versus transmission gate versus Flash-based Multiplexers
• Complex multiplexer structures
• Physical design considerations

5) Configuration storage

• Difference between SRAM memory blocks and configuration storage
• Latches versus flops versus SRAMs
• Booting an FPGA (and pre-initializing states)
• Support for partial reconfiguration
• Configuration readback

6) FPGA Fabric Implementation

• Physical design considerations
• Fabric bootstrapping (from primitives to tiles to fabrics)
• Optimization techniques

7) Elaborating and logic synthesis

• How do we go from behavioural RTL to a netlist?
• Memory and DSP inference overview
• Logic optimization techniques and structures (BDDs, AIGs)
• Flow based LUT mapping

8) Simulators

• Hardware event models
• Compiled (verilator) vs interpreted (iverilog) simulation
• Gate and timing level simulation
• X-propagation models

9) FPGA Technology mapping and routing

• Impact of architectural constraints on placement (fracturable LUTs, shared control sets)
• Placement algorithms: analytical, electrostatic, simulated annealing
• Overview of the routing problem
• Retiming optimisation

10) Negotiation based routing

• A* heuristics
• Congestion cost heuristics
• Timing based routing and rip-up

11) Static Timing Analysis (STA)

• Basics and goals
• Computing setup and hold timing slacks
• Handling of timing constraints (e.g., false paths or multiple clock domains)

12) Bitstream assembly and partial reconfiguration

• Bitstream intermediate formats (FASM)
• Configuration packet formats (Xilinx vs FABulous)
• Bitstream manipulations and applications using the bitstream
• Partial reconfiguration harnesses

13) Design for test robustness and security & Wrap-up

• Radiation hardened FPGAs
• Security features in modern FPGAs
• Wrap-up: 
• What have we learned in ACF? 
• Where does that help us beyond FPGAs?

Exercise 1: Specification of a custom FPGA with customized arithmetic blocks

Exercise 2: Implementation of a negotiation-based router

Project: You will apply the learned material on one (small!) component of the FPGA ecosystem, examples may include:

• Physical FPGA implementation optimizations (designing and characterizing passgate multiplexers, improving switch matrices, improving the wiring, general fabric optimizations
• FPGA primitive optimizations (customization of carry logic, memory blocks, etc.
• A simple simulator
• A simple placer
• Visualization tools